// csr_block.sv — tiny register block with RW, W1C, RO and reserved addresses
module csr_block (
  input  logic       clk,
  input  logic       rst,
  input  logic       wr_en,
  input  logic [1:0] addr,
  input  logic [7:0] wdata,
  output logic [7:0] rdata,      // combinational read of 'addr'
  input  logic       hw_event,   // sets STATUS[0]
  output logic [7:0] ctrl,
  output logic       irq         // = STATUS[0]
);
  always_ff @(posedge clk) begin
    if (rst) begin
      ctrl <= 8'h00;
      irq  <= 1'b0;
    end else begin
      if (wr_en && addr == 2'd0)                  ctrl <= wdata;
      if (hw_event)                               irq  <= 1'b1;   // hardware set wins
      else if (wr_en && addr == 2'd1 && wdata[0]) irq  <= 1'b0;   // write-1-to-clear
    end
  end

  always_comb begin
    case (addr)
      2'd0:    rdata = ctrl;
      2'd1:    rdata = {7'b0, irq};
      2'd2:    rdata = 8'hA5;
      default: rdata = 8'h00;
    endcase
  end
endmodule