// adder_retime.sv — two versions of a registered adder
module adder_reg_out (                       // original: register after the adder
  input  logic       clk, rst,
  input  logic [7:0] a, b,
  output logic [8:0] sum
);
  always_ff @(posedge clk)
    if (rst) sum <= '0;
    else     sum <= a + b;
endmodule

module adder_reg_in (                        // retimed: registers before the adder
  input  logic       clk, rst,
  input  logic [7:0] a, b,
  output logic [8:0] sum
);
  logic [7:0] a_q, b_q;
  always_ff @(posedge clk)
    if (rst) begin a_q <= '0; b_q <= '0; end
    else     begin a_q <= a;  b_q <= b;  end
  assign sum = a_q + b_q;
endmodule