Lesson 3.4 · SystemVerilog Assertions Essentials

Sequences: describing behaviour over time

A sequence is a pattern of Boolean expressions over consecutive clock ticks. Sequences are the building blocks of properties.

Cycle delays: ##n and ##[m:n]

Sequence	Meaning
`a ##1 b`	a, then b on the next tick
`a ##0 b`	a and b on the same tick (sequence fusion)
`a ##3 b`	a, then b exactly 3 ticks later
`a ##[1:4] b`	a, then b 1 to 4 ticks later
`a ##[2:$] b`	a, then b at least 2 ticks later (unbounded)

start ##[1:4] done matches: start at cycle 1, done at cycle 4 (3 ticks later, within 1..4).

Repetition

Operator	Name	Meaning	Example
`b[*3]`	consecutive	b on 3 consecutive ticks	`busy[*3]`
`b[*2:4]`	consecutive range	b on 2 to 4 consecutive ticks	`req[*1:8]`
`b[->2]`	goto	b true twice (not necessarily consecutive); ends on the 2nd b	`ack[->2]`
`b[=2]`	non-consecutive	Like goto, but the match may extend past the 2nd b while b is false	`retry[=2]`

cmd ##1 beat[->2] — after cmd, wait for the second beat (cycles 2 and 4). The sequence ends exactly at cycle 4.

Combining sequences

Operator	Meaning
`s1 and s2`	Both match, starting together; may end at different times (ends at the later one)
`s1 intersect s2`	Both match, starting and ending together
`s1 or s2`	At least one matches
`e throughout s`	Boolean e holds on every tick while s matches
`s1 within s2`	s1 matches somewhere inside a match of s2
`first_match(s)`	Only the earliest match of s is kept

named sequence

// A burst: 'busy' must stay high from start until done, which comes within 2..6 ticks
sequence s_burst;
  start ##1 (busy throughout (##[1:5] done));
endsequence

c_burst: cover property (@(posedge clk) s_burst);